The present invention is directed to a high speed multiplier logic circuit and more particularly to a 4 .times. 4 multiplier using 4 bit threshold logic type adders.
Almost all parallel multipliers are designed around adders which are arranged to minimize the number of addition levels required and thereby optimize operation delay. A further improvement is achieved by the use of carry-look ahead circuits. However, with larger size multipliers such as 4 .times. 4 or 8 .times. 8 the operation delay is excessive.